Description of the Related Art
As gate length decreases, proportions of conventional semiconductor devices that are defective may increase due to hot carrier effects. Hot carrier effects may result from a relatively strong electric field in a drain region. Conventionally, methods for reducing voltage levels, increasing a gate length and/or reducing an impurity density of a drain region may be used to suppress such hot carrier effects. These methods, however, may degrade circuit performance. Alternatively, a field relaxation transistor may be inserted to suppress hot carrier effects.
FIG. 1 is a circuit diagram illustrating a logic circuit including a conventional field relaxation transistor. Referring to FIG. 1, a signal path 20 represents a path through which an input signal IN may pass until being input to the logic circuit 10. The signal path 20 may be configured in various ways depending on a type of the input signal IN or a semiconductor device in which the logic circuit 10 is employed. The conventional logic circuit 10 may include a PMOS transistor P1 connected between a terminal to which a voltage (e.g., a relatively high voltage) Vpp is applied and an output terminal. The PMOS transistor P1 may have a gate to which the input signal IN may be input through the signal path 20. The conventional logic circuit 10 may further include an NMOS transistor N1 connected to a ground voltage. The NMOS transistor N1 may have a gate to which the input signal IN may be input through the signal path 20. The logic circuit 10 may further include an NMOS transistor N2 connected between the output terminal and the NMOS transistor N1. The NMOS transistor N2 may have a gate to which the voltage Vpp may be applied.
The logic circuit 10 may invert the input signal IN input through the signal path 20 to output an output signal OUT. For example, when the input signal IN has a low logic level, the PMOS transistor P1 may be activated or turned on, and the NMOS transistor N1 may be deactivated or turned off, so that the output signal OUT of the high voltage Vpp level is output. When the input signal IN has a high logic level, the PMOS transistor P1 may be deactivated, and the NMOS transistor N1 may be activated, so that the output signal OUT of the ground voltage level may be output. A drain voltage of the NMOS transistor N1 may be reduced by a threshold voltage of the NMOS transistor N2, thereby reducing hot carrier effects.
The logic circuit of FIG. 1 may insert the NMOS transistor N2 between the PMOS transistor P1 and the NMOS transistor N1 as the field relaxation transistor to reduce the drain voltage of the NMOS transistor N1, thereby reducing hot carrier effects.
FIG. 2 is a cross-sectional view illustrating a configuration of the conventional logic circuit of FIG. 1. In FIG. 2, “A”, “B” and “C” denote gates of the PMOS transistor 1 and the NMOS transistors, respectively, “D” denotes a drain region of the NMOS transistor N1, and “STI” denotes a shallow trench isolation for component isolation.
As shown in FIG. 2, the conventional logic circuit may continuously apply the voltage Vpp to the gate B of the NMOS transistor N2. If the input signal IN having a high logic level is applied, a signal of a high logic level is applied to the gate C of the NMOS transistor N1, so that the NMOS transistor N1 is activated and a voltage of the drain region D of the NMOS transistor N1 becomes a ground voltage level. At this time, because the voltage Vpp is applied to the gate B of the NMOS transistor N2, a leakage current 1 may occur due to tunneling, so that the NMOS transistor N2 may deteriorate, causing a circuit malfunction. If the input signal IN having a low logic level is applied, a signal of a low logic level is applied to the gate A of the PMOS transistor P1, so that the PMOS transistor P1 is activated, and the voltage Vpp is applied to the gate B of the NMOS transistor N2, so that the NMOS transistor N2 is activated. Thus, a voltage of the drain region D of the NMOS transistor N1 becomes a voltage level close to the voltage Vpp level. As a result, hot carriers may be generated in the drain region D of the NMOS transistor N1 due to a gate-induced drain leakage (GIDL) or impact ionization. The hot carriers may be accelerated by the voltage Vpp applied to the gate B of the NMOS transistor N2 to induce a gate leakage current 2, so that the NMOS transistor N2 may deteriorate, causing a circuit malfunction.
As described above, in the conventional logic circuit, the voltage Vpp may be continuously applied to the gate B of the NMOS transistor N2, causing deterioration of the NMOS transistor N2 and/or a circuit malfunction.